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_______________ge ne ra l de sc ript ion the max783 is a system-engineered power-supply cont roller for notebook computers or similar battery-powered e quipment. it provides two high-performance step-down (buck) p ulse- width modulators (pwms) for +3.3v/+5v and dual pcmc ia vpp outputs powered by an integral flyback winding controller. other functions include dual, low-dropout, micropow er linear regulators for cmos/rtc back up, and two precision low- battery-detection comparators. high efficiency (95% at 2a, greater than 80% at loa ds from 5ma to 3a) is achieved through synchronous rectific ation and pwm operation at heavy loads, and idle-mode tm oper- ation at light loads. the max783 uses physically s mall components, thanks to high operating frequencies (300khz/200khz) and a new current-mode pwm architec - ture that allows for output filter capacitors as sm all as 30f per ampere of load. line- and load-transient respo nses are terrific, with a high 60khz unity-gain crossove r frequen- cy that allows output transients to be corrected wi thin four or five clock cycles. low system cost is achieved through a high level of integration and the use of low-cost external n-channel mosfets. the integral flyback winding co n- troller provides a low-cost, +15v high-side output that regu- lates even in the absence of a load on the main out put. other features include low-noise, fixed-frequency p wm operation at moderate to heavy loads and a synchron izable oscillator for noise-sensitive applications such as electro- magnetic pen-based systems and communicating comput - ers. the max783 is similar to the max782, except t he fly- back winding is on the 3.3v inductor instead of the 5v inductor, the vpp outputs can be optionally program med to 3.3v, and the device may be completely shut down. ________________________applic a t ions notebook computers portable data terminals communicating computers pen-entry systems ____________________________fe a t ure s ? dual pwm buck controllers (+3.3v and +5v) ? dual pcmcia vpp outputs (0v/3.3v/5v/12v) ? two precision comparators or level translators ? power-ready status output ( rdy5 ) ? 95% efficiency ? optimized for 6-cell applications ? 420a quiescent current;70a in standby (linear regulators alive) 25a shutdown current ? 5.5v to 30v input range ? small ssop package ? fixed output voltages available: 3.3v (standard)3.45v (high-speed pentium ? ) 3.6v (powerpc ? ) ______________orde ring i nform a t ion m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ________________________________________________________________ maxim integrated products 1 ca ll t oll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 for fre e sa m ple s or lit e ra t ure . ? idle-mode is a trademark of maxim integrated produc ts. pentium is a trademark of intel. powerpc is a trademark of ibm. 19-0045; rev 1; 5/94 evaluation kit information included max783 5.5v to 30v vpp control on3 on5 sync power section suspend power low-battery warning vpp (0v/3.3v/5v/12v) p memory peripherals +3.3v +5v dual pcmcia slots 4 vpp (0v/3.3v/5v/12v) shdn _______typic a l applic a t ion dia gra m 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ss3 cs3 fb3 dh3 lx3 bst3 lx5 dl3 v+ vl fb5 pgnd dl5 bst5 sync ref gnd vppb vdd vppa rdy5 q1 q2 vh d2 d1 shdn on3 ssop top view max783 22 21 20 19 15 16 17 18 on5 dh5 cs5 ss5 db0 db1 da0 da1 __________________pin configura t ion 36 ssop 0c to +70c max783rcbx 36 ssop 0c to +70c max783cbx pin-package temp. range part 3.45v 3.3v v out ordering information continued on last page. downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 2 _______________________________________________________________________________________ v+ to gnd .......................................... .......................-0.3v, +36v pgnd to gnd........................................ ................................2v vl to gnd .......................................... .........................-0.3v, +7v bst3, bst5 to gnd .................................. ................-0.3v, +36v lx3 to bst3........................................ .........................-7v, +0.3v lx5 to bst5........................................ .........................-7v, +0.3v inputs/outputs to gnd (d1, d2, s h d n C , on5, ref, sync, da1, da0, db1, db0, on5, ss5, cs5, fb5, r d y 5 C , cs3, fb3, ss3, on3). -0.3v, (vl + 0.3v) vdd to gnd......................................... ........................-0.3v, 20v vppa, vppb to gnd.................................. ...-0.3v, (vdd + 0.3v) vh to gnd .......................................... .........................-0.3v, 20v q1, q2 to gnd...................................... ..........-0.3v, (vh + 0.3v) dl3, dl5 to pgnd................................... .......-0.3v , (vl + 0.3v) dh3 to lx3 ......................................... .........-0.3v, (bst3 + 0.3v) dh5 to lx5 ......................................... .........-0.3v, (bst5 + 0.3v) ref, vl, vpp short to gnd.......................... ..............momentary ref current........................................ .................................20ma vl current ......................................... ..................................50ma vppa, vppb current ................................. ........................100ma continuous power dissipation (t a = +70c) ssop (derate 11.76mw/c above +70c) ............... ....762mw operating temperature ranges: max783cbx/max783_cbx............................... ..0c to +70c max783ebx/max783_ebx ..............................- 40c to +85c storage temperature range .......................... ...-65c to +160c lead temperature (soldering, 10sec) ................ .............+300c electrical characteristics (v+ = 15v, gnd = pgnd = 0v, i vl = i ref = 0ma, s h d n C = on3 = on5 = 5v, other digital input levels are 0v or +5v, t a = t min to t max , unless otherwise noted.) stresses beyond those listed under absolute maximu m ratings may cause permanent damage to the device . these are stress ratings only, and functional operation of the device at these or any other condi tions beyond those indicated in the operational sec tions of the specifications is not implied. exposur e to absolute maximum rating conditions for extended per iods may affect device reliability. absolute maximum ratings vdd = 18v, on3 = on5 = 5v, vppa/vppb programmed to 0v 0mv < (cs5-fb5) < 70mv, 6v < v + < 30v (includes load and line regulation) program to 0v, 13v < vdd < 19v, 0ma < i l < 0.3ma program to 3.3v, 13v < vdd < 19v, 0ma < i l < 60ma program to 5v, 13v < vdd < 19v, 0ma < i l < 60ma program to 12v, 13v < vdd < 19v, 0ma < i l < 60ma vdd = 18v, on3 = on5 = 5v, vppa/vppb programmed to 12v with no external load vdd = 20v cs3-fb3 (vdd < 13v, flyback mode) either controller (0mv to 70mv) either controller (6v to 30v) rising edge, hysteresis = 1% cs3-fb3 or cs5-fb5 falling edge, hysteresis = 1% conditions v 4.80 5.08 5.20 -0.30 0.30 fb5 output voltage 3.17 3.30 3.43 v 5.5 30 4.85 5.05 5.20 v 11.60 12.10 12.50 vppa/vppb output voltage input supply range a 15 30 off vdd current a ma 140 300 2 ss3/ss5 fault sink current quiescent vdd current ma 23 a 2.5 4.0 6.5 ss3/ss5 source current -50 -100 -160 vdd shunt current % v 2.5 load regulation %/v 0.03 18 20 line regulation mv vdd shunt setpoint 80 100 120 v current-limit voltage units 13 14 min typ max vdd regulation setpoint parameter 3.17 3.35 3.46 3.32 3.50 3.60 0mv < (cs3-fb3) < 70mv, 6v < v + < 30v (includes load and line regulation) v 3.46 3.65 3.75 fb3 output voltage max783 max783r max783s 3.3v and 5v step-down controllers 15v flyback controller pcmcia regulators (note 1) downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs _______________________________________________________________________________________ 3 parameter quiescent power consumption (both controllers on) min typ max 5.2 8.6 units mw input current off v+ current 1 a ref fault lockout voltage 30 60 s h d n C , on3, on5, da0, da1, db0, db1, v in = 0v or 5v 2.4 3.2 v ref output voltage 3.24 3.36 a v vl - 0.5 4.2 4.7 v v sync input high voltage 2.4 ref load regulation 30 75 mv s h d n C , on3, on5, da0, da1, db0, db1 d1, d2 trip voltage shutdown v+ current input low voltage 0.8 25 40 1.61 1.69 a standby v+ current v v 70 110 a d1, d2 input current s h d n C , on3, on5, da0, da1, db0, db1, sync 100 na q1, q2 r d y 5 C source current vl output voltage 12 20 30 a q1, q2 r d y 5 C sink current 92 95 200 500 1000 % a q1, q2, r d y 5 C output high voltage sync = 0v or 5v vh - 0.5 v q1, q2, r d y 5 C output low voltage maximum duty cycle 4.5 5.5 v 89 92 0.4 v quiescent vh current vl fault lockout voltage 41 0 a sync = 3.3v 3.6 4.2 v oscillator sync range oscillator frequency 240 350 270 300 330 khz 170 200 230 khz conditions d1 = d2 = d3 = da0 = da1 = db0 = db1 = 0v, fb5 = cs5 = 5.25v, fb3 = cs3 = 3.5v fb5 = cs5 = 5.25v, vl switched over to fb5 falling edge no external load (note 2) rising edge of fb5, hysteresis = 1% sync rise/fall time 0ma < i l < 5ma (note 3) falling edge, hysteresis = 1% C s h d n C = d1 = d2 = on3 = on5 = da0 = da1 = db0 = db1 = 0v, v+ = 30v d1 = d2 = on3 = on5 = da0 = da1 = db0 = db1 = 0v, v+ = 30v d1 = d2 = 0v to 5v vh = 15v, v out = 2.5v vh = 15v, v out 2.5v i source = 5a, vh = 3v on5 = on3 = 0v, 5.5v < v+ < 30v, 0ma < i l < 25ma i sink = 20a, vh = 3v vh = 18v, d1 = d2 = 5v, no external load falling edge, hysteresis = 1% sync = 3.3v sync = 0v or 5v 200 ns not tested sync low pulse width 200 ns sync high pulse width 200 ns electrical characteristics (continued) (v+ = 15v, gnd = pgnd = 0v, i vl = i ref = 0ma, s h d n C = on3 = on5 = 5v, other digital input levels are 0v or +5v, t a = t min to t max , unless otherwise noted.) vl/fb5 switchover voltage (also r d y 5 C trip voltage) internal regulator and reference comparators oscillator and inputs/outputs downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 4 _______________________________________________________________________________________ note 1: output current is further limited by maximum allowa ble package power dissipation. note 2: because the reference uses vl as its supply, the re f line regulation error is insignificant. note 3: the main switching outputs track the reference volt age. loading the reference reduces the main output s slightly according to the closed-loop gain (av cl ) and the reference voltage load regulation error. av cl for the +3.3v supply is unity gain. av cl for the +5v supply is 1.54. max183 5 50 1m 60 100 10 80 70 10m 1 90 100m efficiency (% ) +5v output current (a) efficiency vs. +5v output current v+ = 15v n1-n4 = irf7101 on3 = low f = 200khz v+ = 6v max183 6 50 1m 60 100 10 80 70 10m 1 90 100m efficiency (% ) +3.3v output current (a) efficiency vs. +3. 3v output current v+ = 15v n1-n4 = irf7101 on3 = on5 = high f = 200khz v+ = 6v 500 0 05 2 0 m axim um +15v vdd output current vs. supply voltage 100 200 supply voltage (v) maximum +15v load current (ma) 10 15 vdd > +13v +3.3v regulating +3.3v load = 0a +3.3v load = 3a 300 400 quiescent supply current vs. supply voltage quiescent supply current (ma) 0 1 2 13 14 0 6 12 18 24 30 supply voltage (v) on3 = on5 = high standby supply current vs. supply voltage standby supply current (ma) 0 0.5 1.0 1.5 2.0 2.5 0 6 12 18 24 30 on3 = on5 = 0v supply voltage (v) __________________________________________typic a l o pe ra t ing cha ra c t e rist ic s (circuit of figure 1, transpower tti5902 transforme r, t a = +25c, unless otherwise noted.) parameter conditions units dl3/dl5 sink/source current v out = 2v 1 a dh3/dh5 sink/source current bst3-lx3 = bst5-lx5 = 4.5v, v out = 2v 1 a dl3/dl5 on-resistance high or low 7 dh3/dh5 on-resistance high or low, bst3-lx3 = bst5-lx5 = 4.5v 7 min typ max electrical characteristics (continued) (v+ = 15v, gnd = pgnd = 0v, i vl = i ref = 0ma, s h d n C = on3 = on5 = 5v, other digital input levels are 0v or +5v, t a = t min to t max , unless otherwise noted.) downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs _______________________________________________________________________________________ 5 m inim um v in to v out differential vs. +5v output current minimum v in to v out differential (v) +5v output current (a) 0 0.2 0.4 0.6 0.8 1.0 1m 10m 100m 1 10 300khz 200khz +5v output still regulating 1000 0.1 100 10m 1 switching frequency vs. load current 10 load current (a) switching frequency (khz) 100 1m 100m sync = ref (300khz) on3 = on5 = high +5v, v in = 7.5v 1 +5v, v in = 30v +3.3v, v in = 7.5v ____________________________typic a l ope ra t ing cha ra c t e rist ic s (c ont inue d) (circuit of figure 1, transpower tti5902 transforme r, t a = +25c, unless otherwise noted.) shutdown supply current vs. supply voltage shutdown supply current ( a) 0 100 200 300 400 500 0 61 21 82 43 0 supply voltage (v) shdn = 0v i load = 1a v in = 16v pulse-width m odulation m ode waveform s lx voltage 10v/div +5v output voltage 50mv/div 500ns/div i load = 100ma v in = 10v idle-m ode waveform s +5v output 50mv/div 2v/div 200 s/div downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 6 _______________________________________________________________________________________ i load = 2a +5v line-transient response, falling v in , 16v to 10v 2v/div +5v output 50mv/div 20 s/div v in = 15v +5v load-transient response +5v output 50mv/div 3a 0a load current 200 s/div i load = 2a +5v line-transient response, rising v in , 10v to 16v 2v/div +5v output 50mv/div 20 s/div ____________________________typic a l ope ra t ing cha ra c t e rist ic s (c ont inue d) (circuit of figure 1, transpower tti5902 transforme r, t a = +25c, unless otherwise noted.) 30 10 100 output noise spectrum frequency (khz) output voltage noise (dbmv rms ) -30 -10 10 -20 0 20 1 v in = 10v v out = 5v i out = 50ma 30 100k 1m output noise spectrum -50 frequency (hz) output voltage noise (dbmv rms ) -30 -10 10 -60 -40 -20 0 20 10k v in = 8v to 12v (plots superimposed) v out = 5v i out = 1a downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs _______________________________________________________________________________________ 7 name function 1 on3 on/o f f C control input to disable the +3.3v pwm. tie direct ly to vl for automatic start-up. 2 s h d n C pin ___________________________________________________ ___________pin de sc ript ion 3 d1 4 d2 #2 level-translator/comparator noninverting input ( see d1). 8 r d y 5 C 7 q1 #1 level translator/comparator output (see q2). 6 q2 5 vh external positive supply voltage input for the leve l translators/comparators and r d y 5 C output. 19 on5 on/o f f C control input to disable the +5v pwm supply. tie t o vl for automatic start-up. pcmcia digital control inputs with industry-standar d coding (see table 1). 14 sync 13 ref 12 gnd low-current analog ground. feedback reference poin t for all outputs. 11 vppb 0v, 3.3v, 5v, 12v switchable pcmcia vpp output. so urces 60ma. controlled by db0 and db1. 10 vdd 9 vppa 0v, 3.3v, 5v, 12v switchable pcmcia vpp output. so urces 60ma. controlled by da0 and da1. 20 ss5 soft-start control input for +5v. ramp time to ful l current limit is 1ms/nf of capacitance to gnd. 21 cs5 current-sense input for +5v. current limit level i s +100mv referred to fb5. 22 dh5 gate-drive output for the +5v high-side mosfet. 23 lx5 inductor connection for the +5v supply. 24 bst5 boost capacitor connection for the +5v supply (0.1 f). 25 dl5 gate-drive output for the +5v low-side mosfet. 26 pgnd power ground 15-18 27 fb5 feedback and current-sense input for the +5v pwm. 29 v+ supply voltage input from battery, 5.5v to 30v 28 vl 5v logic supply voltage for internal circuitry. vl is always on and can source 5ma for external loads . 33 dh3 gate-drive output for the +3.3v high-side mosfet. 32 lx3 inductor connection for the +3.3v supply. 31 bst3 boost capacitor connection for the +3.3v supply (0. 1f). 30 dl3 gate-drive output for the +3.3v low-side mosfet. 36 ss3 soft-start input for +3.3v. ramp time to full curr ent limit is 1ms/nf of capacitance to gnd. 35 cs3 current-sense input for +3.3v, current limit level is +100mv referred to fb3. 34 fb3 feedback and current-sense input for the +3.3v pwm. da1, da0, db1, db0 shutdown control input, low-true logic. tie to vl for automatic start-up. the 5v vl supply stays act ive in shutdown. don't force s h d n C higher than vl + 0.5v. #2 level-translator/comparator output. sources 20 a from vh when d2 is high. sinks 500a to gnd when d2 is low, even with vh = 0v. power-good indication for the main +5v supply. low indicates greater than 4.5v at the +5v output. swings 0v to vh. +15v flyback input (feedback). a weak shunt regula tor conducts 3ma to gnd when vdd exceeds 19v. vdd serves as the supply input for the vpp linear r egulators. 3.3v reference output sources up to 5ma for externa l loads. bypass to gnd with 1f/ma of load or 0.22f minimum oscillator control/synchronization input. connect to vl or gnd for 200khz; connect to ref for 300khz. for external clock synchronization in the 240khz to 350khz range, a high-to-low transition starts a ne w cycle. #1 level-translator/comparator noninverting input, threshold = +1.650v. controls q1. tie to gnd if unused. downloaded from: http:///
m ax 7 8 3 _______________de t a ile d de sc ript ion the max783 converts a 5.5v to 30v input to six outp uts (figure 1). it produces two high-power, pwm switch- mode supplies, one at +5v and the other at +3.3v. t he two supplies operate at either 300khz or 200khz, al low- ing for small external components. output current c apa- bility depends on external components, and can exce ed 6a on each supply. two 12v vpp outputs, an internal 5v, 25ma supply (vl) and a 3.3v, 5ma reference voltage are also generated via linear regulators (figure 2) . fault- protection circuitry shuts off the pwm and high-sid e sup- ply when the internal supplies lose regulation. two precision voltage comparators are also included . their output stages permit them to be used as level translators for driving external n-channel mosfets in load-switching applications, or for more convention al logic signals. the max783 is capable of accepting input voltages from 5.5v to 30v, but is optimized for the lower en d of this range because the +15v flyback winding control ler is appended to the +3.3v buck supply. this architec ture allows for lower input voltages than are possible w ith the max782 sister chip, which puts the winding on the + 5v side, while maintaining high +15v load capability. however, the max783s transformer has a higher turn s ratio (4:1 vs. 2:1), which leads to higher interwin ding capacitance as well as higher switching noise ampli - tudes at the transformer secondary when the input v olt- age is high. therefore, the max783 standard applica - tion circuit is optimized with external components for low-voltage (6-8 cell) designs with maximum input v olt- ages of 20v and less. the max783 itself can easily accept 30v inputs, but expect to see more noise and higher voltage swings at the transformer secondary under these conditions. the inductor and filter cap acitor values may also require some adjustment for inputs greater than 20v; see the design procedure section. +5 v sw it c h-m ode supply the +5v supply is generated by a current-mode pwm step-down regulator using two n-channel mosfets, a rectifier, plus an lc output filter (figure 1). the gate- drive signal to the high-side mosfet, which must exceed the battery voltage, is provided by a boost cir- cuit that uses a 100nf capacitor connected to bst5. the +5v supplys dropout voltage, as configured in figure 1, is typically 400mv at 2a. as v+ approach es 5v, the +5v output falls with v+ until the vl regul ator output hits its undervoltage lockout threshold at 4 v. at this point, the +5v supply turns off. a synchronous rectifier at lx5 keeps efficiency hig h by effectively clamping the voltage across the rectifi er diode. maximum current limit is set by an external low- value sense resistor, which prevents excessive indu ctor current during start-up or under short-circuit cond itions. programmable soft-start is set by an optional exter nal capacitor; this reduces in-rush surge currents upon start-up and provides adjustable power-up times for power-supply sequencing purposes. +3 .3 v sw it c h-m ode supply the +3.3v output is produced by a current-mode pwm step-down regulator similar to the +5v supply. the +3.3v supply uses a transformer primary winding as its in duc- tor; the secondary is used for the 15v vdd supply. the default switching frequency for both pwm contro llers is 200khz (with sync connected to gnd or vl), but 300khz may be used by connecting sync to ref. +3 .3 v a nd +5 v pwm buc k cont rolle rs the two current-mode pwm buck controllers are nearl y identical except for different preset output voltag es and the addition of a flyback winding control loop to t he 3.3v side. each pwm is independent, except both are synchronized to a master oscillator and share a com - mon reference (ref) and logic supply (vl). each pwm can be turned on and off separately via on3 and on5 . the pwms are a direct-summing type, lacking a tradi - tional integrator-type error amplifier and the phas e shift associated with it. they therefore do not require e xter- nal feedback compensation components if you follow the filter capacitor esr guidelines in the design procedure . the main gain block is an open-loop comparator that sums four input signals: output voltage error signa l, current-sense signal, slope-compensation ramp, and precision reference voltage. this direct-summing method approaches the ideal of cycle-by-cycle contr ol of the output voltage. under heavy loads, the contr oller operates in full pwm mode. every pulse from the osc il- lator sets the output latch and turns on the high-s ide switch for a period determined by the duty factor (approximately v out /v in ). as the high-side switch turns off, the synchronous rectifier latch is set; 60ns l ater, the low-side switch turns on. the low-side switch stays on until the beginning of the next clock cycle (in con tinu- ous mode) or until the inductor current crosses thr ough triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 8 _______________________________________________________________________________________ table 1. truth table for vpp control pins d_0 d_1 vpp 0 0 0v 0 1 5v 1 0 12v 1 1 3.3v downloaded from: http:///
zero (in discontinuous mode). under fault condition s when the inductor current exceeds the 100mv current - limit threshold, the high-side latch resets and the high- side switch turns off. at light loads, the inductor current fails to excee d the 25mv threshold set by the minimum current compara- tor. when this occurs, the pwm goes into idle mode, skipping most of the oscillator pulses in order to reduce the switching frequency and cut back switching loss es. the oscillator is effectively gated off at light lo ads because the minimum current comparator immediately resets the high-side latch at the beginning of each cycle, unless the fb_ signal falls below the refere nce voltage level. a flyback winding controller regulates the +15v vdd supply in the absence of a load on the main 3.3v ou t- put. if vdd falls below the preset +13v vdd regulat ion threshold, a 1s one-shot is triggered that extends the low-side switchs on-time beyond the point where th e inductor current crosses zero (in discontinuous mod e). this causes inductor (primary) current to reverse, pulling current out of the output filter capacitor and causing the flyback transformer to operate in the f or- ward mode. the low impedance presented by the transformer secondary in forward mode allows the +15v filter capacitor to be quickly charged up agai n, bringing vdd into regulation. m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs _______________________________________________________________________________________ 9 vppa da0 da1 db0 db1 bst3 dh3 lx3 dl3 cs3 fb3 ss3 on3 on5 shdn vppb vdd bst5 dh5 lx5 dl5 cs5 fb5 ss5 vh d1-d2 q1-q2 9 11 10 24 22 23 25 21 27 20 5 3, 4 7, 6 16 15 18 17 31 33 32 30 35 34 36 1 19 gnd pgnd 29 28 12 26 battery input 5.5v to 30v (note 1) vpp control inputs c1 33 f d1a c10 n1 l1 10 h r1 25m +5v at 3a c3 330 f c4 330 f d2 1n5819 n2 c13 0.01 f +3.3v on/off +5v on/off shutdown c15 1 f c7 4.7 f c8 1 f c9 1 f d1b c11 0.1 f d3 ec11fs1 n3 1:4 l2 10 h d5 1n5819 n4 r2 20m c12 2.2 f +3.3v at 3a c14 0.01 f 2 2 comparator supply input comparator inputs comparator outputs oscillator sync +5v at 5ma 0v, 3.3v, 5v, 12v +15v at 200ma, see high-side supply (vdd) section. 0v, 3.3v, 5v, 12v max783 v+ vl c2 33 f c1c6 = sprague 595d or avx tps series n1n4 = si9410dy or irf7101 (both sections) d1a, d1b = low-power schottky (cmpsh3 or equivalent ) for v + < 6v. for v + > 6v, 1n4148 or equivalent is acceptable. note 1: battery voltage range 6v to 20v with components s hown. note 2: keep kelvin-connected current-sense traces short and close together. see fig.5. note 3: zener diode clamp required for vin > 12v. zener can be replaced with 20k pull-down or other 1ma minimum load. (note 2) (note 2) 0.1 f d6 18v 100mw (note 3) c5 150 f c6 150 f 3.3v at 5ma 5v powergood sync ref rdy5 2 8 14 13 figure 1. standard application circuit downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 10 ______________________________________________________________________________________ fb5 cs5 5v pwm controller (see fig. 3) dh5 bst5 lx5 dl5 ss5 fb3 cs3 3.3v pwm controller (see fig. 3) dh3 bst3 lx3 dl3 ss3 on5 on3 +5v ldo linear regulator +3.3v reference 300khz/200khz oscillator vdd q1 q2 v+ vl ref gnd sync vppa da0 da1 vppb db0 db1 d1 d2 vh 1.65v 1.65v linear regulator linear regulator 5v 3.3v 4.5v standby 4v 2.8v 13v to 19v fault on on vdd reg 13v 19v p on pgnd shdn rdy5 max783 on figure 2. block diagram downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 11 shoot- through control r q 60khz lpf minimum current (idle-mode) 25mv r q level shift 1 s single-shot 1x main pwm comparator osc level shift current limit vl 30r 1r 3.3v 4 a synchronous rectifier control 0mv100mv ref, 3.3v (or internal 5v reference) ss_ on_ -100mv vdd reg (see fig. 2) cs_ fb_ bst_ dh_ lx_ vl dl_ pgnd s s slope comp n n n max783 figure 3. pwm controller block diagram downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 12 ______________________________________________________________________________________ soft-start/ss_ inputs connecting capacitors to ss3 and ss5 allows gradual build-up of the +3.3v and +5v supplies after on3 an d on5 are driven high. when on3 or on5 is low, the appropriate ss capacitors are discharged to gnd. when on3 or on5 is driven high, a 4a constant cur- rent source charges these capacitors up to 4v. the resulting ramp voltage on the ss_ pins linearly inc reas- es the current-limit comparator setpoint so as to increase the duty cycle to the external power mosfe ts up to the maximum output. with no ss capacitors, t he circuit will reach maximum current limit within 10 s. soft-start greatly reduces initial in-rush current peaks and allows start-up time to be programmed externall y. synchronous rectifiers synchronous rectification allows for high efficienc y by reducing the losses associated with the schottky re cti- fiers. also, the synchronous rectifier mosfets are necessary for correct operation of the max783's boo st gate-drive and vdd supplies. when the external high-side power mosfet turns off, energy stored in the inductor causes its terminal v olt- age to reverse instantly. current flows in the loo p formed by the inductor, schottky diode, and loadan action that charges up the filter capacitor. the sc hottky diode has a forward voltage of about 0.5v which, although small, represents a significant power loss and degrades efficiency. a synchronous rectifier mosfe t parallels the diode and is turned on by dl3 (or dl5 ) shortly after the diode conducts. since the on res is- tance (r ds(on) ) of the synchronous rectifier is very low, the losses are reduced. the synchronous rectifier mosfet is turned off when the inductor current falls to zero. cross conduction (or shoot-through) occurs if the high- side switch turns on at the same time as the synchr onous rectifier. internal break-before-make timing ensur es that shoot-through does not occur. the schottky rectifi er con- ducts during the time that neither mosfet is on, wh ich improves efficiency by preventing the synchronous-r ectifi- er mosfets lossy body diode from conducting. the synchronous rectifier works under all operating condi- tions, including discontinuous-conduction and idle- mode. the +3.3v synchronous rectifier also controls the 1 5v vdd voltage (see the high-side supply (vdd) section). boost gate-driver supply gate-drive voltage for the high-side n-channel swit ch is generated with a flying-capacitor boost circuit as shown in figure 4. the capacitor is alternately charged f rom the vl supply via the diode and placed in parallel with the high-side mosfets gate-source terminals. on st art- up, the synchronous rectifier (low-side) mosfet for ces lx_ to 0v and charges the bst_ capacitor to 5v. on the second half-cycle, the pwm turns on the high-side mosfet by connecting the capacitor to the mosfet gate by closing an internal switch between bst_ and dh_. this provides the necessary enhancement voltag e to turn on the high-side switch, an action that bo osts the 5v gate-drive signal above the battery voltage. ringing seen at the high-side mosfet gates (dh3 and dh5) in discontinuous-conduction mode (light loads) is a natural operating condition caused by the residua l energy in the tank circuit formed by the inductor a nd stray capacitance at the lx_ nodes. the gate driver negative rail is referred to lx_, so any ringing th ere is directly coupled to the gate-drive supply. modes of operation pwm mode under heavy loadsover approximately 25% of full loadthe +3.3v and +5v supplies operate as continu- ous-current pwm supplies (see typical operating characteristics ). the duty cycle (%on) is approximately: %on = v out /v in current flows continuously in the inductor: first, it ramps up when the power mosfet conducts; then, it ramps down during the flyback portion of each cycle as en ergy is put into the inductor and then discharged into t he load. note that the current flowing into the inductor whe n it is being charged is also flowing into the load, so the load is level translator pwm vl bst_ dh_ lx_ dl_ vl battery input vl figure 4. boost supply for gate drivers downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 13 continuously receiving current from the inductor. this minimizes output ripple and maximizes inductor use, allowing very small physical and electrical sizes. output ripple is primarily a function of the filter capaci tor effec- tive series resistance (esr) and is typically under 50mv (see the design procedure section). output ripple is worst at light load and maximum input voltage. idle mode under light loads (<25% of full load), efficiency i s fur- ther enhanced by turning the drive voltage on and o ff for only a single clock period, skipping most of th e clock pulses entirely. asynchronous switching, see n as ghosting on an oscilloscope, is thus a normal ope rating condition whenever the load current is less than approximately 25% of full load. at certain input voltage and load conditions, a tra nsition region exists where the controller can pass back an d forth from idle-mode to pwm mode. in this situatio n, short bursts of pulses occur that make the current waveform look erratic, but do not materially affect the output ripple. efficiency remains high. current limiting the voltage between cs3 (cs5) and fb3 (fb5) is cont in- uously monitored. an external, low-value shunt res istor is connected between these pins, in series with the inductor, allowing the inductor current to be conti nuously measured throughout the switching cycle. whenever this voltage exceeds 100mv, the drive voltage to th e external high-side mosfet is cut off. this protect s the mosfet, the load, and the battery in case of short cir- cuits or temporary load surges. the current-limiti ng resistor r1 (r2) is typically 25m (20m ) for a 3a load current. oscillator frequency; sync input the sync input controls the oscillator frequency. connecting sync to gnd or to vl selects 200khz oper a- tion; connecting to ref selects 300khz operation. sync can also be driven with an external 240khz to 350kh z cmos/ttl source to synchronize the internal oscilla tor. 300khz operation is used to minimize the inductor a nd filter capacitor sizes, but 200khz may be necessary for low input voltages (see low-voltage operation ). h igh-side supply (v dd) the 15v vdd supply is obtained from the rectified a nd filtered secondary of transformer l2. vdd is enabl ed whenever the +3.3v supply is on (on3 = high). the primary and secondary of l2 are connected so that, during the flyback (discharge) portion of each cycl e, energy stored in the core is transferred into the + 3.3v load through the primary and into vdd through the s ec- ondary, as determined by the turns ratio. the sec- ondary voltage is added to the +3.3v to make vdd. see the typical operating characteristics for the vdd supplys load capability. unlike other coupled-inductor flyback converters, t he vdd voltage is regulated regardless of the loading on the +3.3v output. (most coupled-inductor converter s can only support the auxiliary output when the main output is loaded.) when the +3.3v supply is lightl y loaded, the circuit achieves good control of vdd by pulsing the mosfet normally used as the synchronous rectifier. this draws energy from the +3.3v supply s output capacitor and uses the transformer in a forw ard- converter mode (i.e., the +15v output takes energy out of the secondary when current is flowing in the pri ma- ry). these forward-converter pulses are interspers ed with normal synchronous-rectifier pulses, and they only occur at light loads on the +3.3v rail. the transformer secondarys rectified and filtered out- put is only roughly regulated, and may be between 1 3v and 19v. it is brought back into vdd, which is als o the feedback input, and used as the source for the pcmc ia vpp regulators. it can also be used as the vh power supply for the comparators or any external mosfet drivers. when the input voltage is above 12v, or when the +3.3v supply is heavily loaded and vdd is lightly loaded, l2s interwinding capacitance and leakage inductance can produce voltages above that calculat - ed from the turns ratio. a 2.5ma shunt regulator l imits vdd to 19v. if the battery voltage can rise above 12v, vdd must either be externally clamped with an 18v zener diode, or there must be a 1ma minimum load on vdd (or vppa/vppb). clock-frequency noise on the vdd rail of up to 3v p-p is a facet of normal operation, and can be reduced by adding more output capacitance. pcm ci a-com pa t ible , progra m m a ble v pp supplie s two independent linear regulators furnish pcmcia vp p supplies. the vppa and vppb outputs can be pro- grammed to deliver 0v, 3.3v, 5v, or 12v. the 0v ou t- put mode has a 250 pull-down to discharge external filter capacitors and ensure that flash eproms cann ot be accidentally programmed. these linear regulator s draw their power from the high-side supply (vdd), a nd each can furnish up to 60ma. bypass vppa and vppb to gnd with at least 1f, with the bypass capacitor s less than 20mm from the vpp pins. the outputs are programmed with da0, da1, db0 and db1, as shown in table 2. downloaded from: http:///
m ax 7 8 3 these codes are compatible with many popular pcmcia digital controllers such as the intel 82365sl. for other interfaces, one of the inputs can be permanently wi red high or low and the other toggled to turn the suppl y on and off. the truth table shows that either a 0 o r 1 can be used to turn each supply on. the two vpp output s can be safely connected in parallel for increased load capabil- ity if the control inputs are also tied together (i .e., da0 to db0, da1 to db1). if vpaa and vppb are connected in parallel, some devices may exhibit several milliamp s of increased quiescent supply current when enabled, du e to slightly mismatched output voltage set points. com pa ra t ors two noninverting comparators can be used as preci- sion voltage comparators or high-side drivers. the supply for these comparators (vh) is brought out an d may be connected to any voltage between +3v and +19v. the noninverting inputs (d1-d2) are high imp ed- ance, and the inverting input is internally connect ed to a 1.650v reference. each output (q1-q2) sources 20a from vh when its input is above 1.650v, and sinks 500a to gnd when its input is below 1.650v. the q1-q2 outputs can be fixed together in wired-or configuration since the pull-up current is only 20 a. connecting vh to a logic supply (5v or 3v) allows t he comparators to be used as low-battery detectors. f or dri- ving n-channel power mosfets to turn external loads on and off, vh should be 6v to 12v higher than the loa d volt- age. this enables the mosfets to be fully turned o n and results in low r ds(on) . vdd is a convenient source for vh. i nt e rna l v ref a nd v l supplie s an internal linear regulator produces the 5v used b y the internal control circuits. this regulators output is avail- able on pin vl and can source 5ma for external load s. bypass vl to gnd with 4.7f. to save power, when th e +5v switch-mode supply is above 4.5v, the vl linear regulator is turned off and the high-efficiency +5v switch-mode supply output is internally connected t o vl. the 3.3v precision reference (ref) is powered from the internal 5v vl supply. it can furnish up to 5ma for exter- nal loads. bypass ref to gnd with 0.22f, plus 1f/ ma of load current. the main switch-mode outputs track the reference voltage. loading the reference reduces th e main output voltages slightly, according to the ref erence voltage load regulation error. both the vl and ref supplies can remain activeeven when the switch-mode regulators are turned offto s upply memory keep-alive power (see shutdown mode section). these linear regulator outputs can be directly conn ected to the corresponding switch-mode regulator outputs (i.e., ref to +3.3v, vl to +5v) to hold up the main suppli es in standby mode. however, to ensure start-up, standby load currents must not exceed 5ma on each supply. shut dow n m ode shutdown (s h d n C = low) forces both pwms off and dis- ables the ref output and the auxiliary comparators including r d y 5 C . supply current in shutdown mode is typically 25a. the vl supply remains active and ca n source 25ma for external loads. vl load capability is higher in shutdown and standby modes than when the pwms are operating (25ma vs. 5ma). standby mode is achieved by holding on3 and on5 low while s h d n C is high. this disables both pwms, but keeps vl, ref, and the precision comparators alive. supply current in standby mode is typically 70a. other ways to shut down the max783 are suggested in the applications section of the max782 data sheet. __________________de sign proc e dure figure 1s predesigned application circuit contains the correct component values for 3a output currents and a 6v to 20v input range. use the design procedure tha t follows to optimize this basic schematic for differ ent voltage or current requirements. before beginning a design, firmly establish the fol lowing: v in(max) , the maximum input (battery) voltage. this value should include the worst-case conditions unde r which the power supply is expected to function, suc h as no-load (standby) operation when a battery charg er is connected but no battery is installed. v in(max) can- not exceed 30v. v in(min) , the minimum input (battery) voltage. this value should be taken at the full-load operating cu r- rent under the lowest battery conditions. if v in(min) is below about 6v, the filter capacitance required to maintain good ac load regulation increases, and the current limit for the +5v supply has to be increase d for the same load level. triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 14 ______________________________________________________________________________________ table 2. vpp program codes da0 da1 vppa 0 1 0 1 0v 5v 12v 3.3v 0 0 1 1 db0 db1 vppb 0 0 1 1 0 1 0 1 0v 5v 12v 3.3v downloaded from: http:///
+5 v i nduc t or (l1 ) three inductor parameters are required: the induct ance value (l), the peak inductor current (i lpeak ), and the coil resistance (r l ). the inductance is: (v out ) (v in(max) - v out ) l = (v in(max) ) (f) (i out ) (lir) where: v out = output voltage, 5v v in(max) = maximum input voltage (v) f = switching frequency, normally 300khz i out = maximum +5v dc load current (a) lir = ratio of inductor peak-to-peak ac current to average dc load current, typically 0.3. a higher value of lir allows smaller inductance, bu t results in higher losses and higher ripple. the highest peak inductor current (i lpeak ) equals the dc load current (i out ) plus half the peak-to-peak ac inductor current (i lpp ). the peak-to-peak ac inductor current is typically chosen as 30% of the maximum d c load current, so the peak inductor current is 1.15 times i out . the peak inductor current at full load is given by: (v out ) (v in(max) - v out ) i lpeak = i out + (2) (f) (l) (v in(max) ) the coil resistance should be as low as possible, preferably in the low milliohms. the coil is effec tively in series with the load at all times, so the wire loss es alone are approximately: power loss = (i out 2 )(r l ) in general, select a standard inductor that meets t he l, i lpeak , and r l requirements (see tables 3 and 4). if a standard inductor is unavailable, choose a core wit h an li 2 parameter greater than (l)(i lpeak 2 ), and use the largest wire that will fit the core. +3 .3 v t ra nsform e r (l2 ) table 3 lists two commercially available transforme rs and parts for a custom transformer. the following instructions show how to determine the transformer parameters required for a custom design: l p , the primary inductance value i lpeak , the peak primary current li 2 , the cores energy rating r p and r s , the primary and secondary resistances n, the primary-to-secondary turns ratio. the transformer primary is specified just as the +5 v inductor, using v out = +3.3v; but the secondary output (vdd) power must be added in as if it were part of the primary. vdd current (i dd ) usually includes the vppa and vppb output currents. the total +3.3v power, p total , is the sum of these powers: p total = p3 + p dd where: p3 = (v out ) (i out ); p dd = (vdd) (i dd ); and: v out = output voltage, 3.3v; i out = maximum +3.3v load current (a); vdd = vdd output voltage, 15v; i dd = maximum vdd load current (a); so: p total = (3.3v x i out ) + (15v x i dd ) and the equivalent +3.3v output current, i total , is: i total = p total / 3.3v = [(3.3v x i out ) + (15v x i dd )] / 3.3v. the primary inductance, l p , is given by: (v out ) (v in(max) - v out ) l p = (v in(max) ) (f) (i total ) (lir) where: v in(max) = maximum input voltage f = switching frequency, normally 300khz i total = maximum equivalent load current (a) lir = ratio of primary peak-to-peak ac current to average dc load current, typically 0.3. the highest peak primary current (i lpeak ) equals the total dc load current (i total ) plus half the peak-to-peak ac primary current (i lpp ). the peak-to-peak ac primary current is typically chosen as 30% of the maximum d c load current, so the peak primary current is 1.15 t imes i total . a higher value of lir allows smaller inductance, but results in higher losses and higher ripple. the peak current in the primary at full load is giv en by: (v out ) (v in(max ) - v out ) i lpeak = i total + . (2) (f) (l p) (v in(max) ) choose a core with an li 2 parameter greater than (l p ) (i lpeak 2 ). the winding resistances, r p and r s , should be as low as possible, preferably in the low milliohms. use the largest gauge wire that will fit on the core. the coil is effectively in series with the load at all times, s o the resistive losses in the primary winding alone are approximately (i total ) 2 (r p ). the minimum turns ratio, n min , is 3.3v:(15v-3.3v). use 1:4 to accommodate the tolerance of the +3.3v suppl y. a greater ratio will reduce efficiency of the vpp reg ulators. minimize the diode capacitance and the interwinding capacitance, since they create losses through the vdd shunt regulator. these are most significant wh en the input voltage is high, the +3.3v load is heavy, and there is no load on vdd. m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 15 downloaded from: http:///
m ax 7 8 3 ensure the transformer secondary is connected with the right polarity: a vdd supply will be generated wit h either polarity, but proper operation is possible only wit h the cor- rect polarity. test for correct connection by obse rving the phase relationship between the lx3 switching node a nd the transformer secondary under load. the two wave - forms must be 180 out of phase. current-sense resistors (r1, r2) the sense resistors must carry the peak current in the inductor, which exceeds the full dc load current. the internal current limiting starts when the volta ge across the sense resistors exceeds 100mv nominally, 80mv minimum. use the minimum value to ensure adequate output current capability: for the +5v su p- ply, r1 = 80mv / (1.15 x i out ); for the +3.3v supply, r2 = 80mv/(1.15 x i total ), assuming that lir = 0.3. since the sense resistance values (e.g., r1 = 25m for i out = 3a) are similar to a few centimeters of narrow traces on a printed circuit board, trace resistance can contribute significant errors. to prevent this, ke lvin connect the cs_ and fb_ pins to the sense resistors ; use separate traces not carrying any of the inducto r or load current, as shown in figure 5. run these trac es parallel at minimum spacing from one another. the wiring layout for these traces is critical for stab le, low- ripple outputs (see the layout and grounding section). m osfet sw it c he s (n 1 -n 4 ) the four n-channel power mosfets are usually identi - cal and must be logic-level fets; that is, they m ust be fully on (have low r ds(on) ) with only 4v gate-source drive voltage. the mosfet r ds(on) should ideally be about twice the value of the sense resistor. mosfe ts with even lower r ds(on) have higher gate capacitance, which increases switching time and transition losse s. mosfets with low gate-threshold voltage specifica- tions (i.e., maximum v gs(th) = 2v rather than 3v) are preferred, especially for high-current (5a) applica tions. out put filt e r ca pa c it ors (c3 Cc6 ) the output filter capacitors determine the loop sta bility and output ripple voltage. to ensure stability, th e mini- mum capacitance and maximum esr values are: v ref c f > (v out ) (r cs ) (2) ( ) (gbwp) and, (v out ) (r cs ) esr cf < v ref where: c f = output filter capacitance, c6 or c7 (f) v ref = reference voltage, 3.3v v out = output voltage, 3.3v or 5v r cs = sense resistor ( ) gbwp = gain-bandwidth product, 60khz esr cf = output filter capacitor esr ( ). be sure to select output capacitors that satisfy both the minimum capacitance and maximum esr require- ments. to achieve the low esr required, it may be appropriate to use a capacitance value 2 or 3 times larger than the calculated minimum. the output ripple in continuous-current mode is: v out(rpl) = (i lpp(max) ) [(esr cf +1/(2 x x f x c f )]. in idle-mode, the ripple has a capacitive and resis tive component: (4 x 10 -4 ) (l) v out(rpl) (c) = x (r cs 2 ) (c f ) 1 1 ( + ) volts v out v in - v out (0.02) (esr cf ) v out(rpl) (r) = - volts r cs the total ripple, v out(rpl) , can be approximated as fol- lows: if v out(rpl) (r) < 0.5 v out(rpl) (c), then v out(rpl) = v out(rpl) (c), otherwise, v out(rpl) = 0.5 v out(rpl) (c) + v out(rpl) (r). triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 16 _______________________________________________________________________________________ max783 kelvin sense traces sense resistor main current path fat, high-current traces figure 5. kelvin connections for the current-sense resistors downloaded from: http:///
diode d3 the voltage rating of d3 should be at least 4 x v in + 5v plus a safety margin. a rating of at least 100v is necessary for the maximum 20v supply. use a high- speed silicon diode (with a higher breakdown voltag e and low capacitance) rather than a schottky diode. d3s current rating should exceed twice the maximum current load on vdd. diode s d2 a nd d5 use 1n5819s or similar schottky diodes. d2 and d5 conduct only about 3% of the time, so the 1n5819s 1a current rating is conservative. the voltage rating of d2 and d5 must exceed the maximum input supply volt- age from the battery. these diodes must be schottk y diodes to prevent the lossy mosfet body diodes from turning on, and they must be placed physically clos e to their associated synchronous rectifier mosfets. soft -st a rt ca pa c it ors (c1 3 , c1 4 ) a capacitor connected from gnd to either ss pin cau s- es that supply to ramp up slowly. the ramp time to full current limit, t ss , is approximately 1ms for every nf of capacitance on ss_, with a minimum value of 10s. typical capacitor values are in the 10nf to 100nf r ange. because this ramp is applied to the current-limit c ircuit, the actual time for the output voltage to ramp up depends on the load current and output capacitor value. using figure 1s circuit with a 2a load and no ss capacitor, full output voltage is reached in les s than 1ms after on_ is driven high. bypa ss ca pa c it ors input filter capacitors (c1, c2) use at least 3f/w of output power for the input fi lter capacitors, c1 and c2. they should have less than 150m esr, and should be located no further than 10mm from n1 and n2 to prevent ringing. connect th e negative terminals directly to pgnd. be careful no t to exceed the surge current ratings of the bypass capa ci- tors. if the battery pack or ac adapter has very l ow output impedance, tantalum capacitors may be dam- aged when initial connection is made. in this situ ation, electrolytic capacitors such as sanyo os-con may be necessary. also, take care that the rms input curr ent of the max783 circuit does not exceed the bypass capacitor ripple current rating. the rms input cur rent (i rms ) can be calculated as shown below: i rms = rms ac input current v out (v in - v out ) = i load C v in low -v olt a ge ope ra t ion low input voltages, such as the 6v end-of-life volt age of a 6-cell nicd battery, place extra demands on th e +5v buck regulator because of the very low input-ou t- put differential voltage. the standard application cir- cuit works well with supply voltages down to 6v; at input voltages less than 6v, the +5v filter capacit or values must be increased. if the minimum battery voltage is 6.5v or higher, the 660f total 5v filte r capacitance can be reduced to 330f. the +5v supplys load-transient response is impaired due to reduced inductor-current slew rate, which is in turn caused by reduced voltage applied across the buck inductor during the high-side switch-on time. so, the +5v output sags when hit with an abrupt load current change, unless the +5v filter capacitor value is increased. only the capac i- tance is affected and esr requirements dont change. therefore, the added capacitance can be supplied by an additional low-cost bulk capacitor i n parallel with the normal low-esr switching-regulato r capacitor. the equation for voltage sag under a step-load change follows: (i step 2 )(l) v sag = (2)(c f ) (v in(min) x dmax - v out ) where dmax is the maximum duty cycle. higher duty cycles are possible when the oscillator frequency i s reduced to 200khz, due to fixed propagation delays through the pwm comparator becoming a lesser part o f the whole period. the tested worst-case limit for d max is 92% at 200khz. lower inductance values can reduc e the filter capacitance requirement, but only at the expense of increased noise at high input voltages (resulting from higher peak currents). m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 17 ) ( downloaded from: http:///
m ax 7 8 3 la yout a nd grounding good layout is necessary to achieve the designed ou t- put power, high efficiency, and low noise. good la yout includes use of a ground plane, appropriate compo- nent placement, and correct routing of traces using appropriate trace widths. the following points are in order of importance: 1. a ground plane is essential for optimum performan ce. in most applications, the power supply is located o n a multilayer motherboard, and full use of the four or more copper layers is recommended. use the top and bottom layers for interconnections, and the inn er layers for an uninterrupted ground plane. 2. keep the kelvin-connected current-sense traces short, close together, and away from switching nodes. see figure 5. important: place the curren t- sense resistors close to the ic (less than 10mm away if possible). 3. place the lx node components n1, n2, d2, and l1 as close together as possible. this reduces resisti ve and switching losses and keeps noise due to ground inductance confined. do the same with the other lx node components n3, n4, d5, and l2. 4. the input filter capacitor c1 should be less than 10mm away from n1s drain. the connecting cop- per trace carries large currents and must be at lea st 2mm wide, preferably 5mm. similarly, place c2 close to n3s drain, and connec t them with a wide trace. 5. keep the gate connections to the mosfets short fo r low inductance (less than 20mm long and more than 0.5mm wide) to ensure clean switching. 6. to achieve good shielding, it is best to keep all high-voltage switching signals (mosfet gate dri- ves dh3 and dh5, bst3 and bst5, and the two lx nodes) on one side of the board and all sensitive nodes (cs3, cs5, fb3, fb5 and ref) on the other side. 7. connect the gnd and pgnd pins directly to the ground plane, which should ideally be an inner laye r of a multilayer board. 8. connect the bypass capacitor c7 very close (less than 10mm) to the vl pin. 9. minimize the capacitance at the transformer sec- ondary. place d3 and c12 very close to each other and to the secondary, then route the output to the ics vdd pin with a short trace. bypass with 0.1f close to the vdd pin if this trace is longer than 50mm. the layout for the evaluation board is shown in the evaluation kit section. it provides an effective, low- noise, high-efficiency example. triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 18 ______________________________________________________________________________________ downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 19 table 3. surface-mount components (see figure 1 for schematic and table 4 for manufac turers' telephone numbers.) note 1: four irf7101s total; each device has both sections connected in parallel. note 2: these transformers have different sizes and pinouts . the max783 ev kit has the correct pad layout for the tti5902 trans- former, but all the transformers listed can be wire d in easily. table 4. surface-mount component suppliers company usa phone [ 1 ] 207-283-1941 [ 1 ] 516-435-1824 [ 1 ] 407-241-9339 [ 1 ] 310-322-3332 [ 1 ] 512-992-3377 [ 1 ] 404-736-3030 [81] 3-3494-7414 [ 1 ] 508-339-5063 [81] 3-3607-5428 [ 1 ] 702-831-3521 (207) 282-5111 (800) 282-4975 (516) 435-1110 (407) 241-7876 (310) 322-3331 (512) 992-7900 (404) 736-1300 (805) 867-2555* (508) 339-8900 (708) 956-0666 (702) 831-0140 factory fax [country code] *distributor avx central semi coiltronics international rectifier irc murata-erie nihon sprague sumida transpower tech. component type manufacturer part number c1, c2 33f, 35v tantalum sprague 595d336x0035r2b c3, c4 330f, 10v tantalum sprague 595dd337x0010r2b c5, c6 150f, 10v tantalum sprague 595d157x0010d2b c7 4.7f 16v tantalum sprague 595d475x0016a c8, c9, c15 1f, 20v tantalum sprague 595d105x0020t c10, c11 0.1f, 16v tantalum murata-erie grm42-6x7r104k50v c12 2.2f, 25v tantalum sprague 595d225x0025b c13, c14 0.01f, ceramic murata-erie grm42-6x7r103k50v d1 dual low-power schottky central semiconductor cmpsh-3a d3 fast silicon rectifier nihon ec11fs1 d2, d5 1n5819 schottky nihon ec10qs04 d6 18v, 100mw zener diode central semiconductor cmpz5248 r1 0.025 smt resistor irc lr2010-01-r025-f r2 0.02 smt resistor irc lr2010-01-r020-f n1-n4 n-channel mosfets international rectifier irf7101 (note 1) l1 10h, 2.5a inductor sumida cdr125-100 l2 10h, 1:4 transformer (note 2) transpower tti5897 (for 3.3v at 1a) 33f, 25v tantalum transpower tti5902 (for 3.3v at 3a) avx tpse336m025r0300 coiltronics ctx03-12210 (for 3.3v at 2a) 330f, 6.3v tantalum avx tpse337m006r0100 220f, 10v tantalum avx tpse227m010r0100 downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 20 ______________________________________________________________________________________ ___________ev k it st a nda rd fe a t ure s ? battery range: 5.5v to 20v* ? load capability: 5v at 3a* 3.3v at 3a*12v at 120ma or 15v at 200ma ? 3.3v and 5v keep-alive linear regulator outputs ? dual pcmcia vpp outputs ? oscillator sync input * for wider input voltage range or higher load curren t, see the design procedure. _________________ev k it de sc ript ion the max783 evaluation kit (ev kit) is a preassemble d and tested demonstration board that embodies the standard application circuit, with some extra pull- up and pull-down resistors needed to set default logic sig- nal levels. the board comes configured to accept ba t- tery voltages between 5.5v and 20v, but it can be reconfigured for voltages between 5.5v and 30v. the maximum voltage for safe operation (20v) is deter- mined by the breakdown voltage rating of the extern al mosfets and input filter capacitor (c1 and c2) volt - age ratings; if these are replaced with high-voltag e devices, the board can tolerate 30v input without d am- age (36v absolute max). load current capability of the standard board is 3a at each main output (5v and 3.3v) and 60ma at each 12v vpp output. load current capability can also be con fig- ured by selecting appropriate external components and sense resistor values, with practical load capa bility up to 7a at each main output and 500ma on the 15v flyback output (see the design procedure for reconfig- uring both load and input voltage capability). all func- tions are controlled by two on-board dipswitches, which can be overridden by external cmos/ttl logic signals if desired (provided the dipswitches are se t to off first). see table 3 for the ev kit components. these compo- nents correspond exactly to figure 1's standard application circuit, with the addition of the follo wing chip resistors (which are required only to set defa ult logic and supply levels). the comparator outputs bo th swing 0v to 5v unless r14 is removed and r12 is installed, in which case their output swing is 0v t o 15v. r3-r11 1m 5% resistors (logic pull-down, usually not needed and not installed in normal applications) r12 open-circuit (no resistor installed) r13 100k 5% chip resistor (sync pull-down, usually shorted out) r14 560 5% resistor (pull-up for comparator sup- ply, usually shorted out or left open) ___________ev k it quic k re fe re nc e connect a stiff (30w or better) bench power supply to the +v in and gnd pads found on the edge of the board. turn up the input voltage to somewhere between 5v a nd 20v. set switches sw2a, sw2b, and sw2c on (if they are not already on), taking the device out of shutd own and turning on the main switching regulators. set s witch sw2d off so that the oscillator is set to 200khz, w hich is the appropriate frequency for the 6v-20v input rang e. the main outputs are now regulating and ready for h eavy loads. for best output accuracy and noise character is- tics, loads should be returned separately to the gnd pad corresponding to and adjacent to each output (+3out and +5out). normal full-load regulation error is typically - 2.5% while keeping the outputs with- in tolerance. if the measured error is higher, ther e may be drops in the wiring or ground. ensure the voltme ter is sensing directly at the output and ground pads. to observe normal pwm switching action, place a 1a load on either output and observe the corresponding switching node (device lx_ pin) while varying the i nput voltage. without a load, the switching waveforms ar e intermittent and difficult to trigger on and it may appear that the board isnt working (except for the presen ce of output voltage). to exercise the vpp controls, first ensure the 3.3v switch-mode supply is on. the loosely regulated fly - back voltage (13v to 19v) will be present at the ed ge pad marked +15out. turn on each vpp output by setting the appropriate code on sw1, where on = hig h (see table 1). the 5v linear regulator output is always present, e ven in shutdown mode, and can be measured at the vl pad. i f the battery is connected and vl is not at 5v or clo se to it, something is wrong (excess vl load, possibly). the preci- sion 3.3v linear regulator (ref) is activated by ta king the device out of shutdown mode (by turning sw2c on). turning on the sw2d sets the oscillator to 300khz, but the external component values should be changed fir st (see the design procedure ). the oscillator can be syn- chronized to an external clock signal by driving th e sync pad with a 240khz to 350khz pulse train of 5v amplitude while sw2d is off. ______________________________________________ eva lua t ion k it i nform a t ion downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 21 figure 6. max783 ev kit schematic max783 n3 vppa vppb 31 10 11 9 vppa vppb vdd bst3 28 29 v+ vl d1b 33 dh3 32 lx3 c11 0.1 f n4 +15out d3 c12 2.2 f l2 10 h d6 18v c5 150 f c6 150 f d5 30 dl3 35 cs3 +3.3out 34 fb3 c14 0.01 f 36 ss3 r12 open r14 560 to vl 5 vh 8 rdy5 7 q1 6 q2 vh rdy5 q1 q2 14 sync 13 ref sync ref r13 100k c15 1 f sw2d pgnd gnd 12 26 bst5 db0 dh5 lx5 dl5 cs5 fb5 18 24 22 23 25 21 27 c10 0.1 f n1 n2 d2 l1 10 h r2 20m r1 25m c3 330 f c4 330 f +5out da0 16 da1 15 db1 17 db0 da0 da1 db1 a bc d r5 r4 r6 r3 d1a a bc r11 r10 r9 sw2 sw1 +v in c1 33 f ss5 20 on3 1 on5 19 shdn 2 d1 3 on3 on5 shdn d1 d2 r8 r7 r3 - r11 = 1m vl c2 33 f c7 4.7 f c8 1 f c9 1 f c13 0.01 f 4 d2 downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 22 ______________________________________________________________________________________ figure 7. max783 ev kit top component layout and s ilk screen, top view downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 23 figure 8. max783 ev kit ground plane (layers 2 and 3), top view downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 24 ______________________________________________________________________________________ figure 9. max783 ev kit top layer (layer 1), top v iew downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 25 figure 10. max783 ev kit, bottom component layout and silk screen, bottom view downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 26 ______________________________________________________________________________________ figure 11. max783 ev kit, bottom layer (layer 4), top view downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 27 figure 12. max783 ev kit, drill schedule downloaded from: http:///
m ax 7 8 3 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs maxim cannot assume responsibility for use of any c ircuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the cir cuitry and specifications without notice at any tim e. 28 __________________m a x im i nt e gra t e d produc t s, 1 2 0 sa n ga brie l drive , sunnyva le , ca 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0 ? 1994 maxim integrated products printed usa is a reg istered trademark of maxim integrated products. l dim a a1 b c d e e h l min 0.094 0.004 0.011 0.009 0.604 0.292 0.398 0.020 0? max 0.104 0.011 0.017 0.012 0.610 0.298 0.416 0.035 8? min 2.39 0.10 0.30 0.23 15.34 7.42 10.10 0.51 0? max 2.64 0.28 0.44 0.32 15.49 7.57 10.57 0.89 8? inches millimeters 36-pin plastic shrink small-outline package h e d a a1 c 0.127mm 0.004in. b 0.80 bsc 0.032 bsc 21-0032a e ___________________________________________________ _____pa c k a ge i nform a t ion ___________________chip topogra phy _orde ring i nform a t ion (c ont inue d) lx5 bst5 sync d2 da0 da1 0. 181" (4. 597mm) 0. 132" (3. 353mm) db0 db1 ss5 dh5 on5 cs5 dl5 pgnd fb5 vl v+ dl3 bst3 lx3 ref gnd vppb vdd vppa rdy5 q1 q2 vh d1 shdn on3 ss3 cs3 fb3 dh3 transistor count: 1569 substrate connected to gnd * dice are specified at +25c only. 3.45v 3.6v max783rebx -40c to +85c 36 ssop max783sebx -40c to +85c 36 ssop v out 3.6v 3.3v part temp. range pin-package max783scbx 0c to +70c 36 ssop max783c/d 0c to +70c dice* max783ebx -40c to +85c 36 ssop ev kit temp. range board type 0c to +70c surface mount max783evkit-so downloaded from: http:///

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